1. Field of Invention
The invention relates to a circuit for receiving differential signals and to a digital system including such a circuit.
2. Discussion of the Related Art
It is known to transmit differential digital (normally binary) signals via line pairs, for example twisted line pairs between digital equipment, for example between computers or parts of a computer system. One standard for the transmission of digital signals, the IEEE Standard for Low-Voltage Differential Signals for SCI (LVDS)', draft 1.00 IEEE Std 1596.3-1994, December 1993, requires that differential transmission equipment transmits signals with differential voltages of +/- 250 mV to +/- 400 mV and a common mode voltage of 1.2 V, with a possible deviation of .+-.0.75 mV, and frequencies of up to 622 MHz. Reception equipment has to be capable of receiving these signals with an extended common mode range of between 0-2.4 V to take account of, for example, differences in the ground potential of different pieces of equipment.
FIG. 1 illustrates an example of an interconnection between a first computer 10 and a second computer 12 via a paired cable 14. The first computer 10 includes a transmitter Tx 16 for transmitting differential binary signals via the paired cable 14 to a receiver Rx 18 at the second computer 12. Likewise, the second computer 12 includes a transmitter Tx 20 for transmitting differential signals via the paired cable 22 to a receiver Rx 24 at the first computer 12.
FIG. 2A illustrates an example of a transmitted differential signal, with differential voltages of +/- 250 mV to +/- 400 mV and a common mode of 1.2 V with a deviation of .+-.75 mV.
It will be noted that FIG. 1 represents that the second computer 12 has a ground potential in a range of -1.2 to +1.2 volts compared to the ground potential of the first computer 10. FIG. 2B represents that the receiver must be capable of receiving the transmitted signal with a common mode voltage in the range of 0 V to 2.4 V, that is .+-.1.2 V with respect to the transmitting computer. The need to detect the digital signals when the common mode is over a range of 2.4 volts poses problems where the supply voltage of the receiver circuitry is 3 volts as the 2.4 volt range approaches the supply voltage.
Typically, a conventional differential voltage comparator circuit as illustrated, for example, in FIG. 3 can only derive a differential digital signal from an input differential digital signal with a common mode range of about half the supply voltage VDD. Thus, in FIG. 3 where VDD is 3 volts, it is possible to detect digital signals with a common mode range of only about 1.5 volts to supply or using the equivalent complementary circuit to detect digital signals with a common mode range of only up to about 1.5 volts. This is not sufficient to meet the LVDS standard. In FIG. 3, T1, T4 and T5 are current supply transistors and T2 and T3 are comparator transistors for the first and second differential signal lines.
One internal proposal for meeting the LVDS standard was to employ a voltage divider to reduce the input voltage range to a differential voltage comparator as shown in FIG. 3. A circuit of this type is illustrated in FIG. 4 where resistors R1 and R2 form a resistive bridge and DC1 represents the differential comparator of FIG. 3. However, not only the common mode range as input to the differential comparator DC1 is reduced, but also the differential signal level. This means that the circuit of FIG. 4 reduces the resolution of the receiver circuit. Moreover, the resistive bridge formed by the resistors R1 and R2 introduces an undesirable current drain.
An alternative internal proposal relates to the arrangement illustrated in FIG. 5 where, in addition to a first differential comparator DC1 as shown in FIG. 3, a second differential comparator DC2 is provided. The second differential comparator DC2 is constructed using the complementary circuit of DC1 so that it detects over a voltage range from 1.5-3 volts. To select between the output of the first and second differential comparators, a third comparator C3 is provided. The third comparator may, as shown, be a simple threshold detector connected to one line of the input line pair, or it could be a further differential comparator connected to both lines of the input line pair. The purpose of the third comparator C3 is to detect whether the common mode is greater than or less than 1.5 volts, and in dependence thereon, to output a signal to a multiplexer M for selecting either the outputs of the first differential comparator DC1 or the outputs of the first differential comparator DC2. This circuit has a significant disadvantage which results from delays in deciding whether to select the outputs from the first or the second differential comparators. This is particularly a problem where the common mode is hovering around the mid-point at 1.5 volts. This circuit is not able, therefore, reliably to meet the LVDS standard.
There is, therefore, a need for a reliable and efficient solution to the detection of differential digital signals with a variable common mode.